CMSC 421 Operating Systems Lecture Notes
(c) 1993 Howard E. Motteler


Paging and Virtual Memory
--------------------------

Basic Idea: 

  - keep some pages in memory
  - keep all pages on disk
  - pages on disk that are also in memory 
    may note be up-to-date


Page Tables
------------

Page tables map pages to page frames 

Each process has its own page table

Problems:

   - the page table can be very large
     2^(bits in page field) entries
   - the mapping must be very fast

Page table entries for each page of virtual memory

   - frame number
   - valid bit     (1 if  the page now in a frame)
   - modified bit  (1 if the page has the page been modified)
   - reference bit (1 if page was recently referenced)
   - may also have protection and caching fields

If the disk image is not contiguous, page table may also
need disk address


Steps in translating virtual to physical addresses
---------------------------------------------------

  - Check that page range is valid
    (if not, report `illegal memory reference'
  - look up page in page table
  - if page is in a frame, build physical address (as before)
  - if page is not in a frame, we have a _page fault_
       - find a free frame
       - copy disk page into the new frame
       - continue

If page is not in physical memory, we must find it on disk

Process control block will contain pointer to process image on
disk

If there is no free frame, must take some page out of a frame;
this is done by the _page replacement algorithm_  (more later)

The process is suspended while a page is being copied into a
frame

This is like a usual context switch, but we must be able to
restart the instruction being executed

Problem:

Instructions may refer to more than one address: 

                  MOV -(R0) (R1)

decrements R0 and copies contents at address in R0 to address R1

If this instruction is interrupted, we can't just restart, if R0
has already been decremented

Need a hardware `undo' for _restartable instructions_

Or RISC instructions, with 1 addr ref per instruction


Performance
------------

Effective access time is approximately

                   (1 - p) * m  +  p * f  

where
    p = prob. of a page fault
    m = memory access time (including page table lookup)
    f = time to process a fault:
        - run page replacement algorithm
        - copy out old page (if changed)
        - copy in a new page


Page table structures
----------------------

With 4K pages and a 32 bit address space, need 1M page table
entries

           total bytes = 2^32
           ------------------   =  2^20  =  1 M
           bytes/page  = 2^12


A complete page table would then take at least 4 megabytes

The page table can be split into levels to save space

Suppose we divide up our 32 bit virtual address into 3 fields:



      [ figure:  2 level page table w/ 4K pages ]



Note that such a scheme will take _3_ memory accesses 
(2 for tables and 1 at final physical address) 

An associative memory cache is needed

Usually, page table is manipulated at the hardware level

MIPS is an exception--both page table and assoc. memory misses
are handled in software 


Example Paging Schemes
-----------------------

MIPS example is discussed in the text

MIPS is interesting because hardware provides only the assoc.
memory cache

Page table data structures must be maintained by the kernel

Hardware supports a 64 entry assoc. memory page table

OS Kernel for MIPS chip must deal with assoc. memory misses


Inverted Page Tables
---------------------

Idea: keep page table in frame order rather than in page
order

For example:

  - With 64-bit address space, would need 2^52 entries in
    page table with 4-K pages

  - In this case phys mem << virt mem, so might want to keep
    page table in frame order


        [ figure:  inverse page table ]


In an inverse page table miss, we search the table for a
page, but don't find it.

Can use hashing to find frame given page (may be slower)

Multi-level page tables could also be used

Potential table size is a problem; actual table size
may not be